Implementation of Low Power Rail-To-Rail Dynamic Latch Comparator With Modified Adaptive Power Control Technique

Vijay G Savani, N M Devashrayee


this paper presents a modified technique of power reduction for the preamplifier based dynamic latch comparator. The comparator presented in this paper is having a preamplifier, which is followed by a dynamic latch topology. The comparator is having cross coupled latch to achieve high speed and at a same time kickback effect is also reduced. A modified power control technique is presented to minimize the power consumption, having good reduction in the power compared to other technique presented in the literature. The rail to rail input range and low power comparator which can be suitably used in low-to-medium speed Analog to Digital Converters is implemented in 90nm technology using HSPICE. The simulation results have shown that the power consumption of comparator is 916.9μw at the clock frequency of 200MHz and 1V supply voltage with a delay of 80.3ps


MOSFET, Analog to Digital Convertor, Dynamic Latch Comparator, Adaptive Power Control, VLSI

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Copyright (c) 2017 Vijay G Savani, N M Devashrayee

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